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data sheet preliminary product information data sheet mos integrated circuit pd30550 v r 5500 tm 64-/32-bit microprocessor description t he pd30550 (v r 5500) is a member of the v r series tm of risc (reduced instruction set computer) microprocessors. it is a high-performance 64-/32-bit micropr ocessor that employ s the ri sc architecture developed by mips tm . t he v r 5500 allow s selection of a 64-bit or 32-bit bus w i dt h for the sy stem interf ace, and can operate using protocols compatible w i th the v r 5000 series tm and v r 5432 tm . detailed fu n c tio n d escrip tio n s are p r o v id ed in th e ? v r 5500 user?s man u a l (u16044e) us e r ?s ma nua l. be s u re to re a d the ma nua l be fore de s i gning. features ? 64-/32-bit address/dat a multiplexed bus ? bus w i dth selectable during reset ? bus protocol compatibilit y w i th existing products retained ? maximum operating frequency ? 300 mhz product: internal 300 mhz, external 133 mhz 400 mhz product: internal 400 mhz, external 133 mhz ? external/internal multiplic ation factor selectable from 2 to 5.5 by increments of .5 ? conforms to mips i, ii, iii, iv and mips64 instruction sets. instruction set extensions supported include product-sum operation instructi on, rotate instruction, register scan instruction, and instruction for low pow er mode. ? hardw a re debug functions supported are n-w i re and jt ag. ? supply voltage core block: 1.5 v 5% (300 mhz product) 1.6 to 1.7 v (400 mhz product) i/o block: 3.3 v 5%, 2.5 v 5% ? mips 64-bit risc architecture ? high-speed operation processing ? t w o-w a y superscaler super pipeline ? 300 mhz product: 603 mips 400 mhz product: 804 mips ? high-speed translation lookaside buffer (t lb) (48 entries) ? address space ? phy s ical: 36 bits (64-bit bus selected) 32 bits (32-bit bus selected) ? virtual: 40 bits (in 64-bit mode) 31 bits (in 32-bit mode) ? on-chip floating-point unit (f pu) ? supports sum-of-products instructions ? on-chip primary cache memory (instruction/data: 32 kb each) ? 2-w a y set associative ? supports line lock feature document no. u15700ej1v0ds01 (2nd edition) date published september 2002 n cp(k) printed in usa the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2002 2001
data sheet u15700ej1v0ds 2 ? set-topboxes ? raid ? high-end embedded devices, etc. ordering information part number package maximu m operating frequency (mhz) pd30550f2-300-nn1 272-pin plastic bga (c/d advanced type) (29 29) 300 pd30550f2-400-nn1 272-pin plastic bga (c/d advanced type) (29 29) 400 pin configuration ? 272-pin plastic bga (c/d advanced type) (29 29) pd30550f2-300-nn1 pd30550f2-400-nn1 bottom view top view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 aaywvutrpnmlk jhgfedcba abcdefghj klmnprtuvwyaa
data sheet u15700ej1v0ds 3 (1/2) no. pin name no. pin name no. pin name no. pin name a1 v ss b17 sysad27 d12 v ss h4 v dd a2 v ss b18 v dd io d13 sysad31 h18 v ss a3 v dd io b19 v dd io d14 v dd h19 v ss a4 v dd io b20 v ss d15 sysad60 h20 v ss a5 reset# b21 v ss d16 v ss h21 sysad21 a6 preq# c1 v dd io d17 sysad26 j1 syscmd7 a7 validin# c2 v dd io d18 v ss j2 syscmd8 a8 validout# c3 v ss d19 v ss j3 tintsel a9 v ss c4 v ss d20 v dd io j4 int0# a10 sysadc7 c5 v ss d21 v dd io j18 sysad52 a11 sysadc3 c6 v dd e1 syscmd0 j19 sysad20 a12 sysadc1 c7 wrrdy# e2 disdvalido# j20 sysad51 a13 sysadc4 c8 v ss e3 dwbtrans# j21 sysad19 a14 sysad62 c9 sysid1 e4 o3return# k1 int1# a15 sysad30 c10 v dd e18 sysad57 k2 v ss a16 sysad28 c11 sysadc2 e19 sysad25 k3 v ss a17 sysad59 c12 v ss e20 sysad56 k4 v ss a18 v dd io c13 sysad63 e21 sysad24 k18 v dd a19 v dd io c14 v dd f1 syscmd1 k19 v dd a20 v ss c15 sysad29 f2 v ss k20 v dd a21 v ss c16 v ss f3 v ss k21 v dd b1 v ss c17 sysad58 f4 v ss l1 int2# b2 v ss c18 v dd io f18 v dd l2 int3# b3 v dd io c19 v ss f19 v dd l3 int4# b4 v dd io c20 v dd io f20 v dd l4 int5# b5 coldreset# c21 v dd io f21 sysad55 l18 sysad17 b6 release# d1 v dd io g1 syscmd2 l19 sysad49 b7 extrqst# d2 v dd io g2 syscmd3 l20 sysad18 b8 busmode d3 v ss g3 syscmd4 l21 sysad50 b9 sysid2 d4 v ss g4 syscmd5 m1 rmode#/bktgio# b10 v dd d5 ic g18 sysad23 m2 v dd b11 sysadc6 d6 v dd g19 sysad54 m3 v dd b12 v ss d7 rdrdy# g20 sysad22 m4 v dd b13 sysadc0 d8 v ss g21 sysad53 m18 v ss b14 v dd d9 sysid0 h1 syscmd6 m19 v ss b15 sysad61 d10 v dd h2 v dd m20 v ss b16 v ss d11 sysadc5 h3 v dd m21 v ss caution leave the ic pin open. remark # indicates active low.
data sheet u15700ej1v0ds 4 (2/2) no. pin name no. pin name no. pin name no. pin name n1 v dd io t21 sysad12 w2 v dd io y12 v dd n2 nmi# u1 ntrcclk w3 v ss y13 sysad3 n3 v dd io u2 ntrcdata0 w4 v ss y14 v ss n4 bigendian u3 ntrcdata1 w5 v dd pa2 y15 sysad37 n18 sysad15 u4 ntrcdata3 w6 v ss y16 sysad39 n19 sysad47 u18 sysad10 w7 v dd io y17 sysad40 n20 sysad16 u19 sysad42 w8 v dd y18 v dd io n21 sysad48 u20 sysad11 w9 jtdi y19 v dd io p1 v ss u21 sysad43 w10 v ss y20 v ss p2 v ss v1 ntrcdata2 w11 sysad1 y21 v ss p3 v ss v2 ntrcend w12 v dd aa1 v ss p4 v ss v3 v ss w13 sysad35 aa2 v ss p18 v dd v4 v ss w14 v ss aa3 v dd io p19 v dd v5 v ss pa2 w15 sysad38 aa4 v dd io p20 v dd v6 v ss w16 v dd aa5 v dd pa1 p21 sysad46 v7 v dd io w17 sysad9 aa6 v dd io r1 divmode0 v8 v dd w18 v ss aa7 ic r2 divmode1 v9 jtms w19 v ss aa8 jtdo r3 divmode2 v10 v ss w20 v dd io aa9 drvcon r4 v dd io v11 sysad33 w21 v dd io aa10 v ss r18 sysad44 v12 v dd y1 v ss aa11 sysad0 r19 sysad13 v13 sysad4 y2 v ss aa12 sysad2 r20 sysad45 v14 v ss y3 v dd io aa13 sysad34 r21 sysad14 v15 sysad7 y4 v dd io aa14 sysad36 t1 v dd v16 v dd y5 v ss pa1 aa15 sysad5 t2 v dd v17 sysad41 y6 sysclock aa16 sysad6 t3 v dd v18 v ss y7 jtrst# aa17 sysad8 t4 v dd v19 v ss y8 v dd aa18 v dd io t18 v ss v20 v dd io y9 jtck aa19 v dd io t19 v ss v21 v dd io y10 v ss aa20 v ss t20 v ss w1 v dd io y11 sysad32 aa21 v ss caution leave the ic pin open. remarks 1. # indicates active low.
data sheet u15700ej1v0ds 5 bigendian: big endian bktgio#: break/trigger input/output busmode: bus mode coldreset#: cold reset disdvalido#: disable delay validout# divmode(2:0): divide mode drvcon: driver control dwbtrans#: doubleword block transfer extrqst#: external request ic internally connected int(5:0)#: interrupt jtck: jtag clock jtdi: jtag data input jtdo: jtag data output jtms: jtag mode select jtrst#: jtag reset nmi#: non-maskable interrupt ntrcclk: n-trace clock ntrcdata(3:0) : n-trace data output ntrcend: n-trace end o3return#: out-of-order return mode preq#: processor request rdrdy#: read ready release#: release reset#: reset sysad(63:0): system address/data bus sysadc(7:0): system address/data check bus sysclock: system clock syscmd(8:0): system command/data identifier bus sysid(2:0): system bus identifier tintsel: timer interrupt selection validin#: valid input validout#: valid output v dd : power supply for cpu core v dd io: power supply for i/o v dd pa1, v dd pa2: noise sensitive v dd for pll v ss : ground v ss pa1, v ss pa2: noise sensitive v ss for pll wrrdy#: write ready remark # indicates active low.
data sheet u15700ej1v0ds 6 siu sysclock control signal sysad bus (64/32 bits) v r 5500 cp0 fpu/ macu lsu ifu exu fpu icu dcu alu0 wtb test interface clock generator data cache imq rnrf rs rcu instruction cache rb tlb bht ras rf sb bru alu1
data sheet u15700ej1v0ds 7
data sheet u15700ej1v0ds 8 remark # indicates active low. 1.1 list of pin functions (1) system interface signals pin name i/o function sysad(63:0) i/o system address/data bus a 64-bit bus for communication between the proc essor and external agent. the lower 32 bits (sysad(31:0)) are used in 32-bit bus mode. sysadc(7:0) i/o system address/data check bus a bus for sysad bus parity. valid only during a dat a cycle. the lower 32 bits (sysadc(3:0)) are used in 32-bit bus mode. syscmd(8:0) i/o system command/data id bus a 9-bit bus that transfers command and data i dentifiers between the processor and external agent sysid(2:0) i/o system bus protocol id these signals transfer request identifiers in the out-of-order return mode. the processor drives a valid identifier in sync hronization with the activation of the validout# signal. the external agent must drive valid identifiers in synchronization with the activation of the validin# signal. validin# input valid in this signal indicates the external agent is driv ing a valid address or data onto the sysad bus, a valid command or data identifier onto the syscmd bus, or a valid request identifier onto the sysid bus in the out-of-order return mode. validout# output valid out this signal indicates the proce ssor is driving a valid address or data onto the sysad bus, a valid command or data identifier onto the syscmd bus, or a valid request identifier onto the sysid bus in the out-of-order return mode. rdrdy# input read ready this signal indicates the external agent is ready to accept a processor read request wrrdy# input write ready this signal indicates the external agent is ready to accept a processor write request extrqst# input external request this signal indicates the external agent is r equesting the right to use the system interface release# output releases interface this signal indicates the processo r is releasing the system inte rface to external agent control preq# output processor request this signal indicates the proce ssor has a request that is pending
data sheet u15700ej1v0ds 9 (1/2) pin name i/o function divmode(2:0) division mode these signals set the division ratio of pclock and sysclock as follows: 111: 5.5 110: 5 101: 4.5 100: 4 011: 3.5 010: 3 001: 2.5 000: 2 set the input levels of these signals before a power-on reset. make sure that the levels of these signals do not change while the v r 5500 is operating. bigendian input endian mode this signal sets the byte ordering for addressing. 1: big endian 0: little endian set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. busmode input bus mode this signal sets the bus width of the system interface. 1: 64 bits 0: 32 bits set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. tintsel input interrupt source select this signal sets the interrupt source to be a ssigned to the ip7 bit of the cause register. 1: timer interrupt 0: int5# input and external write request (sysad5) set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. disdvalido# input validout# delay enable 1: validout# is active even while the address cycle is stalled 0: validout# is active dur ing the address issuance cycle only set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. dwbtrans# input doubleword block transfer enable (valid in 32-bit bus mode only) 1: disabled 0: enabled set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. remark 1: high level, 0: low level
data sheet u15700ej1v0ds 10 (2/2) pin name i/o function o3return# input out-of-order return mode this signal sets the protocol of the system interface. 1: normal mode 0: out-of-order return mode set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. coldreset# input cold reset this signal completely initializes the internal status of the processor. deassert it in synchronization with sysclock. reset# input reset this signal logically initializes the internal status of the processor. deassert it in synchronization with sysclock. drvcon input drive control this signal sets the impedance of the external output driver. 1: low 0: normal (recommended) set the input level of this signal before a power-on reset. make sure that the level of this signal does not change during vr5500 operation. remark applies to revision 2.0 or later products . fixed to 0 in revision 1.x products. remark 1: high level, 0: low level the o3return#, dwbtrans#, disdvalido#, and busmode signals are used for determining the protocol of the system interface. the protocol is selected as follows in accordance with the setting of these signals. protocol o3return# dwbtrans# disdvalido# busmode v r 5000 tm compatible 1 1 1 1 rm523x compatible 1 1 1 0 v r 5432 native mode compatible 1 0 0 0 out-of-order return mode 0 ar bitrary arbitrary arbitrary remark 1: high level, 0:low level rm523x is a product of pmc-sierra, inc. (3) interrupt interface signals pin name i/o function int(5:0)# input interrupt these are general-purpose processor interrupt r equests. the input states can be checked by the cause register. whether int5# is acknowledged or not depends on the status of the tintsel signal during reset. nmi# input non-maskable interrupt this is the non-maskable interrupt request.
data sheet u15700ej1v0ds 11 pin name i/o function sysclock input system clock clock input to the processor v dd pa1 v dd pa2 ? v dd for pll power supply for the internal pll v ss pa1 v ss pa2 ? v ss for pll ground for the internal pll (5) power supply pin name i/o function v dd ? power supply pin for core v dd io ? power supply pin for i/o v ss ? ground potential pin caution the v r 5500 uses two separate power supply pins. the pow er supply pins can be applied in any sequence. power application to the pins must occur within 100ms of each other. (6) test interface signals pin name i/o function ntrcdata(3:0) output trace data trace data output ntrcend output trace end this signal indicates the end of a trace data packet. ntrcclk output trace clock clock for the test interface. the same clock as sysclock is output. rmode#/ bktgio# i/o reset mode/break trigger i/o when the jtrst# signal is active, th is is a debug reset mode input signal . during normal operation this serves as a break or trigger i/o signal. jtdi input jtag data input serial data input for jtag jtdo output jtag data output serial data output for jtag. output is perform ed in synchronization with the rise of jtck. jtms input jtag mode select this signal selects the jtag test mode. jtck input jtag clock input serial clock input for jtag. the maximum fr equency is 33 mhz. there is no need for it to be synchronized with sysclock. jtrst# input jtag reset input a signal for initializing the jtag test module.
data sheet u15700ej1v0ds 12 (1) system interface pins (a) 32-bit bus mode the v r 5500 allows selection of a sysad bus width from 64 bits or 32 bits. when the 32-bit bus mode is selected, the v r 5500 operates using only the requir ed system interface pins. t herefore, set the unused pins as follows when operating the v r 5500 in the 32-bit bus mode. pin name recommended connection of unused pins sysad(63:32) leave open sysadc(7:4) leave open (b) normal mode the v r 5500 can process read/write transacti ons regardless of the order in which requests are issued in the out-of-order return mode. the sysid( 2:0) signals are used to identify each request during this processing. set these signals, which are not used in the normal mode, as follows. pin name recommended connection of unused pins sysid(2:0) leave open (c) parity bus the v r 5500 allows selection of whether the data is protected using parity. when parity is used, the parity data is output from the processor or external agent to the sysadc bus. however, whether the parity is used or not is selected by software, so unless the program is started, the v r 5500 cannot determine the operat ion of the sysadc bus. therefore, care must be taken to prevent the sysadc bus from being left open or in a high-impedance state. each pin of the sysadc bus should be connected to v dd io via a high resistance value resistor when parity is not used.
data sheet u15700ej1v0ds 13 the v r 5500 can be used to perform testing and debugging via n- wire and jtag with t he device mounted on the board. the test interface pins are used for connection with the exte rnal debug tool during this debugging. when this test interface is not going to be used and when it is in normal operation mode, set the test interface pins as follows. pin name recommended connection of unused pins jtck pull up jtdi pull up jtms pull up jtrst# pull up jtdo leave open ntrcclk leave open ntrcdata(3:0) leave open ntrcend leave open rmode#/bktgio# pull up
data sheet u15700ej1v0ds 14 absolute maximum ratings parameter symbol conditions ratings unit v dd io ? 0.5 to + 4.0 v v dd ? 0.5 to + 2.0 v supply voltage v dd p ? 0.5 to + 2.0 v ? 0.5 to v dd io + 0.3 v input voltage note v i pulse of less than 7 ns ? 1.5 to v dd io + 0.3 v operating case temperature t c ? 10 to + 85 c storage temperature t stg ? 40 to + 125 c note the upper limit of the input voltage (v cc io + 0.3) is +4.0 v. cautions 1. do not short-circuit two or more outputs at the same time. 2. the maximum ratings shown in the table above indicate the point at which the product is on the verge of being physically damaged. exceeding the maximum ratings even momentarily on any parameter may cause such damage. therefore do not use the product under conditions which will violate these ratings. the specifications and conditions shown in the following dc characteristics and ac characteristics sections are the ranges within which the product can normally operate and the quality can be guaranteed. operating conditions (1) 300 mhz product parameter symbol conditions min. max. unit 2.375 2.625 v v dd io 3.135 3.465 v v dd 1.425 1.575 v supply voltage v dd p 1.425 1.575 v caution v dd can also be used with the volt age range of the 400 mhz product (1.6 to 1.7 v). internal operation at 300 mhz is still guaranteed. the core block suppl y current in this case (ma x. 1.8 a) is the same value as the 400 mhz product. (2) 400 mhz product parameter symbol conditions min. max. unit 2.375 2.625 v v dd io 3.135 3.465 v v dd 1.6 1.7 v supply voltage v dd p 1.6 1.7 v caution v dd can also be used with the volt age range of the 300 mhz product (1 .425 to 1.575 v). in this case, internal operation at 300 mhz is guaranteed only. the core block supply cu rrent in this case (max. 1.4 a) is the same value as the 300 mhz product.
data sheet u15700ej1v0ds 15 parameter symbol conditions min. max. unit 300 mhz product, during normal operation, v dd = v dd p = 1.575 v 1.4 a i dd 400 mhz product, during normal operation, v dd = v dd p = 1.7 v 1.8 a 300 mhz product, in standby mode, v dd = v dd p = 1.575 v 0.35 a supply current of core block i dd _sb 400 mhz product, in standby mode, v dd = v dd p = 1.7 v 0.45 a remark the supply current in the i/o block varies dependi ng on the application used. it is normally 20% i dd or lower. dc characteristics (1) when v dd io = 2.5 v ? + ? + parameter symbol conditions min. max. unit output voltage, high v oh v dd io = min., i oh = 4 ma 0.8 v dd io v output voltage, low v ol v dd io = min., i ol = 4 ma 0.4 v input voltage, high note 1 v ih 2.0 v dd io + 0.3 v ? 0.5 0.2 v dd io v input voltage, low note 1 v il pulse of less than 7 ns ? 1.5 0.2 v dd io v input voltage, high note 2 v ihc 0.8 v dd io v dd io + 0.3 v ? 0.5 0.2 v dd io v input voltage, low note 2 v ilc pulse of less than 7 ns ? 1.5 0.2 v dd io v input current leakage, high i lih v i = v dd io 5.0 a input current leakage, low i lil v i = 0 v ? 5.0 a output current leakage, high i loh v o = v dd io 5.0 a output current leakage, low i lol v o = 0 v ? 5.0 a notes 1. does not apply to the sysclock pin. 2. only applies to the sysclock pin.
data sheet u15700ej1v0ds 16 ? + ? + parameter symbol conditions min. max. unit output voltage, high v oh v dd io = min., i oh = 4 ma 2.4 v output voltage, low v ol v dd io = min., i ol = 4 ma 0.4 v input voltage, high note 1 v ih 2.0 v dd io + 0.3 v input voltage, low note 1 ? 0.5 0.8 v v il pulse of less than 7 ns ? 1.5 0.8 v input voltage, high note 2 v ihc 0.8 v dd io v dd io + 0.3 v input voltage, low note 2 ? 0.5 0.2 v dd io v v ilc pulse of less than 7 ns ? 1.5 0.2 v dd io v input current leakage, high i lih v i = v dd io 5.0 a input current leakage, low i lil v i = 0 v ? 5.0 a output current leakage, high i loh v o = v dd io 5.0 a output current leakage, low i lol v o = 0 v ? 5.0 a notes 1. does not apply to the sysclock pin. 2. only applies to the sysclock pin.
data sheet u15700ej1v0ds 17 the v r 5500 uses two power supply pins. these power suppl y pins can be applied in any sequence. however, power may not be applied to one pin more than 100 ms before it is applied to the other. parameter symbol conditions min. max. unit power-on delay t df 0 100 ms capacitance (t a = 25 parameter symbol conditions min. max. unit input capacitance c in 5.0 pf output capacitance c out f c = 1 mhz unmeasured pins returned to 0 v 7.0 pf ac characteristics (300 mhz products: tc = ? 10 to + 85, v dd io = 2.5 v 5%, 3.3 v 5%, v dd = v dd p = 1.5 v 5%) (400 mhz product: tc = ? 10 to + 85, v dd io = 2.5 v 5%, 3.3 v 5%, v dd = v dd p = 1.6 to 1.7 v) clock parameters (1/2) parameter symbol conditions min. max. unit system clock high-level width t ch 1.8 ns system clock low-level width t cl 1.8 ns 300 mhz product 200 300 mhz pipeline clock frequency 400 mhz product 200 400 mhz divmode = 2:1 100 133 mhz divmode = 2.5:1 80 120 mhz divmode = 3:1 66.7 100 mhz divmode = 3.5:1 57.2 85.7 mhz divmode = 4:1 50 75 mhz divmode = 4.5:1 44.5 66.6 mhz divmode = 5:1 40 60 mhz 300 mhz product divmode = 5.5:1 36.4 54.5 mhz divmode = 2:1 100 133 mhz divmode = 2.5:1 80 133 mhz divmode = 3:1 66.7 133 mhz divmode = 3.5:1 57.2 114 mhz divmode = 4:1 50 100 mhz divmode = 4.5:1 44.5 88.8 mhz divmode = 5:1 40 80 mhz system clock frequency note 400 mhz product divmode = 5.5:1 36.4 72.7 mhz note this is the frequency at which the operat ion of the internal pll is guaranteed.
data sheet u15700ej1v0ds 18 parameter symbol conditions min. max. unit divmode = 2:1 7.5 10 ns divmode = 2.5:1 8.3 12.5 ns divmode = 3:1 10 15 ns divmode = 3.5:1 11.7 17.5 ns divmode = 4:1 13.3 20 ns divmode = 4.5:1 15 22.5 ns divmode = 5:1 16.7 25 ns 300 mhz product divmode = 5.5:1 18.3 27.5 ns divmode = 2:1 7.5 10 ns divmode = 2.5:1 7.5 12.5 ns divmode = 3:1 7.5 15 ns divmode = 3.5:1 8.8 17.5 ns divmode = 4:1 10 20 ns divmode = 4.5:1 11.3 22.5 ns divmode = 5:1 12.5 25 ns system clock cycle t cp 400 mhz product divmode = 5.5:1 13.8 27.5 ns system clock jitter t j 5 % system clock rise time t cr 1.2 ns system clock fall time t cf 1.2 ns jtag clock frequency 33 mhz remarks 1. the system clock jitter is a cycle-to-cycle jitter. 2. the jtag clock runs asynchronously to the system clock. system interface parameters parameter symbol conditions min. max. unit data output hold time note 1 t dm 1.0 ns data output delay time note 1 t do 5.0 ns data input setup time note 2 t ds 1.5 ns 300 mhz product 1.0 ns data input hold time note 2 t dh 400 mhz product 0.5 ns notes 1. applies to the release#, validout#, sysad(63:0), sysadc(7:0), syscmd(8:0), and sysid(2:0) pins. 2. applies to the coldreset#, re set#, int(5:0), nmi#, extrqst#, rdrdy#, validin#, sysad(63:0), sysadc(7:0), syscmd(8:0), and sysid(2:0) pins. load coefficient parameter symbol conditions min. max. unit load coefficient cld 1.0 ns/25 pf
data sheet u15700ej1v0ds 19 t do 50% 50% sysclock all output pins t dm load conditions dut all output pins c l = 50 pf timing charts clock timing t cp t ch t cl 50% sysclock t cr t cf 80% 20%
data sheet u15700ej1v0ds 20 t j 50% t j sysclock system interface edge timing t do t dh t dh t do t dm t dm t ds t ds sysclock sysad(63:0), sysadc(7:0), syscmd(8:0), sysid(2:0) validin#, extrqst#, rdrdy#, wrrdy#, int(5:0)#, nmi# coldreset#, reset# validout#, release#, preq# output output input input output output
data sheet u15700ej1v0ds 21 12 34 sysclock (input) cycle pclock (internal) data note (output) note (input) data data data data data data data t ds t dh t dm t do note sysad(63:0), sysadc(7:0), syscmd(8:0), sysid(2:0) power-on sequence t df t df 50% 50% v dd io v dd
data sheet u15700ej1v0ds 22 v dd io v dd 64 k sysclock sysclock (input) 100 ms coldreset# (input) reset# (input) t ds 16 sysclock t ds note 1 note 2 notes 1. 1.425 v (300 mhz product), 1.6 v (400 mhz product) 2. 2.375 v at 2.5v operation or 3.135 v at 3.3v operation cold reset timing v dd io 64 k sysclock sysclock (input) coldreset# (input) reset# (input) t ds 16 sysclock t ds t ds t ds h v dd h
data sheet u15700ej1v0ds 23 h v dd io 16 sysclock sysclock (input) coldreset# (input) reset# (input) t ds t ds h h v dd
data sheet u15700ej1v0ds 24 b a s y s 272-pin plastic bga (cavity down advanced type) (29x29) item millimeters d 29.00 0.20 e 29.00 0.20 a1 0.60 0.10 a2 1.15 e 1.80 a 1.27 ze a4 0.25min. x1 0.30 x2 0.15 b y 0.20 0.75 0.15 zd 1.80 p272f2-127-ba1 a index area e d 4-c1.4 a a2 a1 e a4 detail of a part m m s a b s x2 x1 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 w y aa vutrpnmlk jhgfedcba zd ze b 1.75 0.30
data sheet u15700ej1v0ds 25 this product should be soldered and mounted under the following recommended conditions. for details on the recommended soldering conditions, refer to the semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, cont act an nec sales representative. table 4-1. surface mounting type soldering conditions soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-3 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet u15700ej1v0ds 26 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. reference document electrical characteristics for microcomputer (u15170j) note note this document number is that of japanese version. the related documents indicated in the publication may include preliminary versions. however, preliminary versions are not marked as such.
data sheet u15700ej1v0ds 27 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v?lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290

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